NXP Semiconductors /MIMXRT1021 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_B1_05

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_AD_B1_05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_AD_B1_05 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: USDHC1_WP of instance: usdhc1

1 (ALT1): Select mux mode: ALT1 mux port: FLEXSPI_A_SS0_B of instance: flexspi_bus2bit

2 (ALT2): Select mux mode: ALT2 mux port: LPSPI4_SDI of instance: lpspi4

3 (ALT3): Select mux mode: ALT3 mux port: SAI1_RX_DATA00 of instance: sai1

4 (ALT4): Select mux mode: ALT4 mux port: FLEXIO1_FLEXIO10 of instance: flexio1

5 (ALT5): Select mux mode: ALT5 mux port: GPIO1_IO21 of instance: gpio1

6 (ALT6): Select mux mode: ALT6 mux port: LPSPI1_PCS2 of instance: lpspi1

7 (ALT7): Select mux mode: ALT7 mux port: KPP_ROW06 of instance: kpp

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_B1_05

Links

() ()